WHATS NEW IN 2007.2.2 --------------------- 1. Added support for displaying bound signals as part of the assertion components and can be displayed on the waveform viewer using "Show Assertion Components" WHATS NEW IN 2007.2.1 --------------------- 1. Added support for bus bit in a bind statement 2. Added support for bus bit within a bound module, instead of the whole bus that was specified in the bind statement WHATS NEW IN 2007.2.0 --------------------- 1. Added support for showing SystemVerilog Classes in the hierarchy browser 2. Added support for displaying SystemVerilog Class members as waveforms 3. Added support for annotating the source code window with values for SystemVerilog Class members WHATS NEW IN 2007.1.9 --------------------- 1. Added PLI support for Simucad's Silos Verilog Simulator on 32-bit Red Hat Entr. Linux platform 2. Added support for UT_WRITE_DIR environment variable. If this variable is set, it will open the *.open file in the specified directory. (For network users, setting this variable to point to the local home directory will result in significant speed improvement during waveform viewing) WHATS NEW IN 2007.1.8 --------------------- 1. Inactive license time-out will now try to acquire equivalent license on retry, not just the exact license it had used before 2. Fixed slow loading of designs with memories 3. Fixed CONCAT gates in Schematic to only be used with real Concat instead of Vector signals 4. Fixed $vtDumpvars(levels,scope); to work identical to $dumpvars(levels,scope); WHATS NEW IN 2007.1.7 --------------------- 1. Added support for disabling descend into cell on a cell by cell basis. Also, added support for specifying a gate file name to use for displaying a cell. How to use: ut -iv -vtsymbollib where filename is the cell name to glyph file name mapping file like the .vtcellrc file. If this command line option is specified, it will use the specified file name instead of using the $VTCELLRC_FILE or ~/.vtcellrc The .vtcellrc file has the following format: cell_name cell_name If the optional_gate_file_name is omitted, then the cell will use a glyph similar to the box with pin names that is used for modules. If the optional_gate_file_name is specified, it should be the name of a gate file in the $UT_ROOT_DIR/GATES directory without the .gate file extension. Example .vtcellrc file: SP615NQ ; Use generic box glyph for 6-in, 2-out custom FF MM700TJ NAND ; Use NAND.gate file for NAND gate ZP803LQ NOR ; Use NOR.gate file for NOR gate 2. Added support for new .wlf reader; ModelSim 6.3c 3. Added support for double-clicking a waveform edge with the T0 cursor to do Snap To Source. Removed Snap To Source toggle icon button 4. Added new documentation - 10 Minute Tour of VeritoolsVerifyer - 10 Minute Tour of VeritoolsDesigner - Webex tutorial of VeritoolsDesigner - A section in README_FIRST summarizing the name,description and time-to-read each document 5. Added support for pdf help files. If a help file has a .pdf file extension, it will automatically be loaded into a pdf viewer. It will search for a pdf viewer in the following order: $PDF_READER environment variable, acroread, xpdf WHATS NEW IN 2007.1.6 --------------------- 1. Added support for +VTFLUSHINTERVAL. This will force the file to flush data and be readable at the start of times 1,10,100,1000, 10,000, 100,000, 1,000,000 . This will only work for the +VTCOMPRESS250 (default) and +VTCOMPRESS260 mode 2. Added support for old license names in addition to newer license names. Licenses still need the proper license version number. 3. Added support for a debug log for debug VPI libraries. This is done by setting environment variable VTVPIHVPI_DEBUG_LOG= WHATS NEW IN 2007.1.5 --------------------- 1. Added support for system verilog interfaces to vtVpiDumpvars, source window find drivers/loads, schematic, and assertions. 2. Added support for .hier_separator directive in hsim.out files. WHATS NEW IN 2007.1.4 --------------------- 1. Addded support for structs/unions in source code window, assertions, and schematic. (ncsim 5.8 does not yet support setting callbacks on struct/union members, so it is not yet supported in dumpfiles.) 2. Added support for enums in source code window, assertions, schematic and VPI dumpfiles. 3. Added support for UDP's in schematic so that they are treated as primitives instead of modules. 4. Auto-versioning for PLI/VPI. This will now use the "version_number" of VeritoolsDesigner WHATS NEW IN 2007.1.3 --------------------- 1. Added support for "disable iff" in system verilog assertion properties. WHATS NEW IN 2007.1.2 --------------------- 1. Added support for "+define" to the ut -iv command line. 2. Added support for int, integer, real, and time arrays to the VPI library. 3. Added support for displaying int, integer, real, and time array waveforms. WHATS NEW IN 2007.1.1 --------------------- 1. Added support for key to remove selected signals from the waveform window 2. Added support for standard MS Copy (Ctrl-C), Cut (Ctrl-X), Paste (Ctrl-V) to the waveform window hot keys. To allow this Choose (Ctrl-H) and Scroll To (Ctrl-T) were changed from their previous hot keys (C & V). All of these can be configured in the configuration window. 3. Added support for closing windows with the 'X' button for most windows. 4. Added support for scrolling with the mouse wheel. The mouse pointer must be positioned over the scrollbar for this to work except the waveform window panes will scroll vertically if the pointer is in any portion of the waveform pane that scrolls. 5. Added support for $vtDumpsuppress("name") and $vtVpiDumpsuppress("name"). The "name" can either be a hierarchical module name or a defined module name. The specified module will not be dumped in the dumpfile. $vtDumpsuppress/$vtVpiDumpsuppress calls must be made before the call to $vtDumpvars/$vtVpiDumpvars in order to have any effect. 6. Added $vtVpiDumpflush. WHATS NEW IN 2007.1.0 --------------------- 1. Added support for separate 32, 64, & univ licenses 2. Added $vtVpiDumpname system task to vpi. This can be used to set the name of the dumpfile instead of using the +VTOPTZ_SFILE command line option 3.Added support for shortint, int, longint, byte, bit, logic and enum system verilog data types to vtVpiDumpvars. enum is supported only as a numerical value, and not yet as a label. ncsim does not yet support the shortreal data type 4. Added new memory window that works like a waveform window without waveforms. Window -> Open Window -> Memory in Source Window. Options -> Memory in vWave window WHATS NEW IN 2006.2.0 --------------------- 1. Added support for 'cover property' and 'assume property' in Assertion Analyzer tool 2. Added STARTPERL and ENDPERL pipe i/o commands to pass and execute perl scripts. 3. Added 'libreadutf.a' file reader API library WHATS NEW IN 2006.1.9 --------------------- 1. Added support for Dynamic Transactions 2. Added support for PLI file sizes larger than 2GB. WHATS NEW IN 2006.1.8 --------------------- 1. Added support for system verilog libaries usnig -y and -v flags 2. New shared object library (PLI) for use with Synopsys' VCS simulator WHATS NEW IN 2006.1.7 --------------------- 1. Added compare script files to use the correct file identifier strings WHATS NEW IN 2006.1.5 ----------------------- 1. Added support for Coverage in Assertion Analyzer. 2. Added support for Drivers/Loads in tasks in the Source Window. 3. Added support for states that are not assigned in the State Machine Window. 4. Added support for Descend Into Submodules for Find: Text in the Find Window. WHATS NEW IN 2006.1.4 ----------------------- Changed iv help menus to work the same as the help menu in the waveform window Changed help to first look for firefox browser, then netscape browser Changed help to not busy-wait for the browser to come up Fixed issue while manipulating hierarchy inside source code window WHATS NEW IN 2006.1.3 ----------------------- The Help menu will now look for Netscape browser, and then Mozilla browser. If it can't find either of these browsers, it will open a dialog box saying that it can't find either of these browsers. Users can still goto the directory 'docs' inside the distribution directory and open the Manual for this software or the QuickStart with Adobe Acrobat Reader application. WHATS NEW IN 2006.1.2 ----------------------- 1. Local variables are now also displayed with "Show Assertion Timing with Components" in the Assertion window. 2. Color-coding of the assertion text in the Assertion window now follows the placement of the T0 cursor (just as if "Show Assertion Timing at T0" had been selected.) 3. Added "Show Threads For Selected Timing Waveform" to Options menu in Assertions window. First, select a timing waveform in the waveform window that indicates it has multiple threads (indicated by red down arrow on timing waveform at the time the threads split apart.) Next, select the menu item in the Assertion window. This will bring up a list of threads in the Assertion window that can be selected for display. This process can be repeated to dive down deeper into the next set of threads if the new thread splits apart into yet more threads. 4. Added color-coding of assertion text to the Assertion window (assertion analyzer). The assertion text will color-code based on which assertion result starts at the current value of the T0 cursor (just like the Display Assertion Timing at T0 feature.) This color-coding is automatically done when the assertion is selected in the Assertion window, when the Display Assertion Timing At T0 feature is actived, or when the Display Assertion Timing With Components feature is activated.The portion of the assertion text that is failing for the assertion timing at the T0 cursor will display in red. WHATS NEW IN 2006.1.1 ----------------------- 1. Enhanced support for bussed components in the schematic and concatenated signals 2. Added support for escaped bus bit names to be treated as busses. 3. Fixed crash when there are more than 1024 module definitions. 4. Fixed trouble reading file generated by the hsim API when there is a huge hierarchy in the file. 5. Fixed crash due to unnamed MUX pin. 6. Multiple schematic windows and the state machine brower are now disabled while a schematic is being built. 7. Fixed finding drivers/loads for nets that are declared using ANSI port declarations. 8. Fixed crash due to dangling pins in cells when doing descend into cells in the schematic. 9. Added support for dragging a module definition name from the source window to the schematic. 10. Fixed hang due to elaborating forever statement that looped forever. 11. Double-clicking on module instances in the source window now shows the module definition. Double-clicking on the module definition in the source window now shows the module instance. 12. If the T1 cursor is set to an earlier time than the T0 cursor, it is now used as a limit for auto clock rollback in the Schematic and Control Flow Graph. WHATS NEW IN 2006.1.0 --------------------- 1. Fixed crash evaluating assertions that refer to a property that has been commented out or does not exist 2. Fixed displaying transition information on the schematic for single bits of a bus. 3. Fixed crash when doing Load Batch Run with a design that uses "bind" for modules. 4. Fixed crash for "Display Assertion Timing" without first placing the T0 cursor when there is an assertion clocking event at time 0.