WHATS NEW IN 2008.1.2 1. Schematic now makes room for updating blank values on component pins. 2. Fixed dragging single items from the choose window to single line text areas such as the eye diagram window and the convert to digital window. 3. Added "Standard eye with clock signal" to the eye diagram window. 4. Fixed snap for eye diagram waveforms. 5. The new vdump executable is called vdump2. (A new ut executable is required to read the new vdump2 files.) It supports two new command line arguments: -Z #chunks This tells the vdump2 to make a 280 mode file using the specified number of chunks equivalent to +VTNUMCHUNKS in the PLI. The default is 1 which tells it not to make a 280 mode file. At file read time speed of read will be current time dived by number of chunks, open file will equal current open file size divided by number of chunks. -z #MB_per_chunk This tells the vdump2 the size to use for a compression chunk in megabytes which is equivalent to +VTCHUNKSIZE in the PLI. The default is 16 which tells it to use 16MB per chunk. 6. Added support for making uncompressed fast files over 2GB in size with vdump2. 7. Building ut2008.1.2 on CentOS5-64 Bits WHATS NEW IN 2008.1.1 --------------------- 1. Added support for modeltech fli in libvtvpivhpi_mt.so. 2. "Display Current Drivers" in the source window now uses the expression evaluator to try to find the current driver for the signal. 3. Added several partial update strategies to the schematic window to keep it from slowing down the whole tool. Prior to this feature moving the cursor on the waveform window would be slow if a large schematic with many elements was displayed due to the speed of updating all of these elements. 4. Verified support for SV interfaces and modports. 5. Fixed highlighted nets on the schematic so they are retained when going upscope and downscope. 6. Decoupled module port names from the pins outside of the module so they can be used for selecting restricted nets on downscope in the schematic without affecting other features (highlight net, etc.) 7. Upscope in the schematic will now automatically expand nets that were previously highlighted. 8. Added Options -> Upscope, Show Whole Module to the schematic window. When toggled "on", the Upscope operation will show the whole schematic at the new scope. NOTE: Upscope opertaions: Users can now select a net on a pin of any element going out of this module, and go upscope to see this module and pin and the connections to other gates and modules connected to this pin. Toggeling down the Option => Upscope, Show whole module will show the entire schematic for the upscope module and the selected net in the lower module will be highlighted in the upscope module. Down Scope Operations: Users go down scope by double clicking into the black space inside of any module. If a outside pin on this module is selected, the down scope module will show the entire schematic for that module and also high light the pin that was selected in the upscope module. If a module inside pin is selected, then the user will see only the down scope schematic for that selected pin and the logic connected to just that pin. WHATS NEW IN 2008.1.0 --------------------- 1. Updated the VPI/VHPI to include MTI FLI interface. 2. Added latest parser to vtcom and VeritoolsDesigner 3. Added in trace back for Show Input Cone for schemtics with no signal values. 4. Added in trace back for ito trace ifrom point A on schematic to point B, an instance name of schematic element. WHATS NEW IN 2007.2.5 --------------------- 1. Added ABS function to the Analog Functions window. 2. Added VT_INACTIVE_LIMIT environment variable for setting the number of minutes of inactive time before licenses are released. There is still a 20 hour built-in inactive time limit as well, so setting this environment variable to a value larger than 1200 minutes has no effect (it can only make it shorter.) 3. Added support for reading new +VTCOMPRESS280 mode files. (PLI writer will be a separate commit.) 4. Added support for new +VTCOMPRESS280 mode $vtDumpvars. This file format divides the data into a fixed number of separate chunks. +VTNUMCHUNKS controls the number of chunks to use. Only the first $vtDumpvars() call will be divided into separate chunks. Subsequent $vtDumpvars() calls will each use one new data chunk. +VTNUMCHUNKS10 is the default. +VTCHUNKSIZE can be used to set the size of each uncompressed data chunk in MB. +VTCHUNKSIZE16 is the default (16MB). Examples: % ncsim -f ncsim.args +VTCOMPRESS280 % ncsim -f ncsim.args +VTCOMPRESS280 +VTNUMCHUNKS200 % ncsim -f ncsim.args +VTCOMPRESS280 +VTNUMCHUNKS1000 +VTCHUNKSIZE4 5. Added module filter function to hierarchy window. The filter will now filter the submodule names for the currently selected module. If any submodules are filtered out, the module name will turn red to indicate that what is shown is not a complete hierarchy at that level. Filters are persistent until manually cleared (apply a filter with empty text area) or "Clear All Filters" is selected so that a different filter can be applied to different modules without changing a previous filter. 6. Added "Clear All Filters" to the Actions menu in the hierarchy window. This will clear all of the filters in the hierarchy window. 7. Added a popup window when a request is made to display a schematic for a module containing more than 1000 elements. The operation can then either be continued or cancelled. 8. Added schematic elements limit to UNdertow file: UNdertow.schemElementsLimit: 1000 9. Added "Choose Hierarchy" icon button toggle to schematic window. This will attach a choose window to the side of the schematic. 10. The schematic will no longer descend into FF cells when doing a multi-scope schematic. 11. It is now possible to drag the component instance name from the schematic window (as well as the component itself.) 12. Toggling a component pin now highlights/unhighlights the net whether or not "Highlight Net" icon is toggled. 13. Double-clicking on the name inside a module box will descend into a schematic only showing what is connected to that net. Selecting several names and then double-clicking inside a module box will descend into a schematic showing only the selected nets. 14. Toggling the component instance name in the schematic now toggles the name and highlights/unhighlights the component. 15. Dropping a module/cell instance into the waveform window will display the input and output signals for that module/cell instance. 16. Added support for hot keys in the schematic. Ctrl-C for Copy and Ctrl-V for Paste 17. Support for Ultrasim Wrapper Interface. Ultrasim users can now dump waveform files in Veritools' .fast directly from the the simulator WHATS NEW IN 2007.2.4 --------------------- 1. Support annotation of escaped signal names in source code window WHATS NEW IN 2007.2.3 --------------------- 1. Added "Show Libraries" option to hierarchy window. This needs to be toggled on to show -v and -y files in the hierarchy. (Default: off) 2. Options -> Icons -> Show Net and Options -> Bundle Connections now toggle on/off in separate schematic windows rather than being a global setting. 3. Edit -> Clear will now only clear the current schematic window. 4. Added display of interior udp pin labels when udp's appear in a cell glyph. 5. Options -> Icons -> Show Net will now automatically toggle off after doing Edit -> Clear in a schematic window. 6. In general, a highlighted net in the schematic window should only turn off when its pin is toggled off or when Options -> Icons -> Show Net is toggled off. 7. Highlighted nets/pins will now be highlighted after Options -> Icons -> Upscope in a schematic window. 8. Dragging an escaped module instance name from the source window is now supported. 9. Search for module instance in the Find Window now works for modules instances containing escaped names. 10. The text for inactive modules is now grayed out in the source code window. 11. Back/Forward in the source window now remembers exactly where it was scrolled to before 12. Added performance tweaks to reduce the time updating the source window with a new file/module WHATS NEW IN 2007.2.2 --------------------- 1. Added support for displaying bound signals as part of the assertion components and can be displayed on the waveform viewer using "Show Assertion Components" WHATS NEW IN 2007.2.1 --------------------- 1. Added support for bus bit in a bind statement 2. Added support for bus bit within a bound module, instead of the whole bus that was specified in the bind statement WHATS NEW IN 2007.2.0 --------------------- 1. Added support for showing SystemVerilog Classes in the hierarchy browser 2. Added support for displaying SystemVerilog Class members as waveforms 3. Added support for annotating the source code window with values for SystemVerilog Class members WHATS NEW IN 2007.1.9 --------------------- 1. Added PLI support for Simucad's Silos Verilog Simulator on 32-bit Red Hat Entr. Linux platform 2. Added support for UT_WRITE_DIR environment variable. If this variable is set, it will open the *.open file in the specified directory. (For network users, setting this variable to point to the local home directory will result in significant speed improvement during waveform viewing) WHATS NEW IN 2007.1.8 --------------------- 1. Inactive license time-out will now try to acquire equivalent license on retry, not just the exact license it had used before 2. Fixed slow loading of designs with memories 3. Fixed CONCAT gates in Schematic to only be used with real Concat instead of Vector signals 4. Fixed $vtDumpvars(levels,scope); to work identical to $dumpvars(levels,scope); WHATS NEW IN 2007.1.7 --------------------- 1. Added support for disabling descend into cell on a cell by cell basis. Also, added support for specifying a gate file name to use for displaying a cell. How to use: ut -iv -vtsymbollib where filename is the cell name to glyph file name mapping file like the .vtcellrc file. If this command line option is specified, it will use the specified file name instead of using the $VTCELLRC_FILE or ~/.vtcellrc The .vtcellrc file has the following format: cell_name cell_name If the optional_gate_file_name is omitted, then the cell will use a glyph similar to the box with pin names that is used for modules. If the optional_gate_file_name is specified, it should be the name of a gate file in the $UT_ROOT_DIR/GATES directory without the .gate file extension. Example .vtcellrc file: SP615NQ ; Use generic box glyph for 6-in, 2-out custom FF MM700TJ NAND ; Use NAND.gate file for NAND gate ZP803LQ NOR ; Use NOR.gate file for NOR gate 2. Added support for new .wlf reader; ModelSim 6.3c 3. Added support for double-clicking a waveform edge with the T0 cursor to do Snap To Source. Removed Snap To Source toggle icon button 4. Added new documentation - 10 Minute Tour of VeritoolsVerifyer - 10 Minute Tour of VeritoolsDesigner - Webex tutorial of VeritoolsDesigner - A section in README_FIRST summarizing the name,description and time-to-read each document 5. Added support for pdf help files. If a help file has a .pdf file extension, it will automatically be loaded into a pdf viewer. It will search for a pdf viewer in the following order: $PDF_READER environment variable, acroread, xpdf WHATS NEW IN 2007.1.6 --------------------- 1. Added support for +VTFLUSHINTERVAL. This will force the file to flush data and be readable at the start of times 1,10,100,1000, 10,000, 100,000, 1,000,000 . This will only work for the +VTCOMPRESS250 (default) and +VTCOMPRESS260 mode 2. Added support for old license names in addition to newer license names. Licenses still need the proper license version number. 3. Added support for a debug log for debug VPI libraries. This is done by setting environment variable VTVPIHVPI_DEBUG_LOG= WHATS NEW IN 2007.1.5 --------------------- 1. Added support for system verilog interfaces to vtVpiDumpvars, source window find drivers/loads, schematic, and assertions. 2. Added support for .hier_separator directive in hsim.out files. WHATS NEW IN 2007.1.4 --------------------- 1. Addded support for structs/unions in source code window, assertions, and schematic. (ncsim 5.8 does not yet support setting callbacks on struct/union members, so it is not yet supported in dumpfiles.) 2. Added support for enums in source code window, assertions, schematic and VPI dumpfiles. 3. Added support for UDP's in schematic so that they are treated as primitives instead of modules. 4. Auto-versioning for PLI/VPI. This will now use the "version_number" of VeritoolsDesigner WHATS NEW IN 2007.1.3 --------------------- 1. Added support for "disable iff" in system verilog assertion properties. WHATS NEW IN 2007.1.2 --------------------- 1. Added support for "+define" to the ut -iv command line. 2. Added support for int, integer, real, and time arrays to the VPI library. 3. Added support for displaying int, integer, real, and time array waveforms. WHATS NEW IN 2007.1.1 --------------------- 1. Added support for key to remove selected signals from the waveform window 2. Added support for standard MS Copy (Ctrl-C), Cut (Ctrl-X), Paste (Ctrl-V) to the waveform window hot keys. To allow this Choose (Ctrl-H) and Scroll To (Ctrl-T) were changed from their previous hot keys (C & V). All of these can be configured in the configuration window. 3. Added support for closing windows with the 'X' button for most windows. 4. Added support for scrolling with the mouse wheel. The mouse pointer must be positioned over the scrollbar for this to work except the waveform window panes will scroll vertically if the pointer is in any portion of the waveform pane that scrolls. 5. Added support for $vtDumpsuppress("name") and $vtVpiDumpsuppress("name"). The "name" can either be a hierarchical module name or a defined module name. The specified module will not be dumped in the dumpfile. $vtDumpsuppress/$vtVpiDumpsuppress calls must be made before the call to $vtDumpvars/$vtVpiDumpvars in order to have any effect. 6. Added $vtVpiDumpflush. WHATS NEW IN 2007.1.0 --------------------- 1. Added support for separate 32, 64, & univ licenses 2. Added $vtVpiDumpname system task to vpi. This can be used to set the name of the dumpfile instead of using the +VTOPTZ_SFILE command line option 3.Added support for shortint, int, longint, byte, bit, logic and enum system verilog data types to vtVpiDumpvars. enum is supported only as a numerical value, and not yet as a label. ncsim does not yet support the shortreal data type 4. Added new memory window that works like a waveform window without waveforms. Window -> Open Window -> Memory in Source Window. Options -> Memory in vWave window WHATS NEW IN 2006.2.0 --------------------- 1. Added support for 'cover property' and 'assume property' in Assertion Analyzer tool 2. Added STARTPERL and ENDPERL pipe i/o commands to pass and execute perl scripts. 3. Added 'libreadutf.a' file reader API library WHATS NEW IN 2006.1.9 --------------------- 1. Added support for Dynamic Transactions 2. Added support for PLI file sizes larger than 2GB. WHATS NEW IN 2006.1.8 --------------------- 1. Added support for system verilog libaries usnig -y and -v flags 2. New shared object library (PLI) for use with Synopsys' VCS simulator WHATS NEW IN 2006.1.7 --------------------- 1. Added compare script files to use the correct file identifier strings WHATS NEW IN 2006.1.5 ----------------------- 1. Added support for Coverage in Assertion Analyzer. 2. Added support for Drivers/Loads in tasks in the Source Window. 3. Added support for states that are not assigned in the State Machine Window. 4. Added support for Descend Into Submodules for Find: Text in the Find Window. WHATS NEW IN 2006.1.4 ----------------------- Changed iv help menus to work the same as the help menu in the waveform window Changed help to first look for firefox browser, then netscape browser Changed help to not busy-wait for the browser to come up Fixed issue while manipulating hierarchy inside source code window WHATS NEW IN 2006.1.3 ----------------------- The Help menu will now look for Netscape browser, and then Mozilla browser. If it can't find either of these browsers, it will open a dialog box saying that it can't find either of these browsers. Users can still goto the directory 'docs' inside the distribution directory and open the Manual for this software or the QuickStart with Adobe Acrobat Reader application. WHATS NEW IN 2006.1.2 ----------------------- 1. Local variables are now also displayed with "Show Assertion Timing with Components" in the Assertion window. 2. Color-coding of the assertion text in the Assertion window now follows the placement of the T0 cursor (just as if "Show Assertion Timing at T0" had been selected.) 3. Added "Show Threads For Selected Timing Waveform" to Options menu in Assertions window. First, select a timing waveform in the waveform window that indicates it has multiple threads (indicated by red down arrow on timing waveform at the time the threads split apart.) Next, select the menu item in the Assertion window. This will bring up a list of threads in the Assertion window that can be selected for display. This process can be repeated to dive down deeper into the next set of threads if the new thread splits apart into yet more threads. 4. Added color-coding of assertion text to the Assertion window (assertion analyzer). The assertion text will color-code based on which assertion result starts at the current value of the T0 cursor (just like the Display Assertion Timing at T0 feature.) This color-coding is automatically done when the assertion is selected in the Assertion window, when the Display Assertion Timing At T0 feature is actived, or when the Display Assertion Timing With Components feature is activated.The portion of the assertion text that is failing for the assertion timing at the T0 cursor will display in red. WHATS NEW IN 2006.1.1 ----------------------- 1. Enhanced support for bussed components in the schematic and concatenated signals 2. Added support for escaped bus bit names to be treated as busses. 3. Fixed crash when there are more than 1024 module definitions. 4. Fixed trouble reading file generated by the hsim API when there is a huge hierarchy in the file. 5. Fixed crash due to unnamed MUX pin. 6. Multiple schematic windows and the state machine brower are now disabled while a schematic is being built. 7. Fixed finding drivers/loads for nets that are declared using ANSI port declarations. 8. Fixed crash due to dangling pins in cells when doing descend into cells in the schematic. 9. Added support for dragging a module definition name from the source window to the schematic. 10. Fixed hang due to elaborating forever statement that looped forever. 11. Double-clicking on module instances in the source window now shows the module definition. Double-clicking on the module definition in the source window now shows the module instance. 12. If the T1 cursor is set to an earlier time than the T0 cursor, it is now used as a limit for auto clock rollback in the Schematic and Control Flow Graph. WHATS NEW IN 2006.1.0 --------------------- 1. Fixed crash evaluating assertions that refer to a property that has been commented out or does not exist 2. Fixed displaying transition information on the schematic for single bits of a bus. 3. Fixed crash when doing Load Batch Run with a design that uses "bind" for modules. 4. Fixed crash for "Display Assertion Timing" without first placing the T0 cursor when there is an assertion clocking event at time 0.