Whats new in ut2008.1.4

1. Fixed hierarchically connected vector signal waveforms

2. Fixed hierarchical name listing for any signal



Whats new in ut2008.1.3

1. Added major speed up to the Veritools VPI, PLI by removing callbacks for signals that are unconnected or do not change.

2. Added additional speeds ups by optimizing  VPI code

3. Added SuSe 32 bit port

4. Added CentOS 5  both 64 bit and 32 bit ports

5. Added a libvtvpi_vcs.so port for Verilog only VCS

6. Fixed static declaration of memory file calls to work with VCS simulator.

7. Veritools work around for single +incdir+ command line option, use multiple +incdir+ command line options if user wants more than one +incdir+:
 
      +incdir+dir1 +incdir+dir2 +incdir+dir3

8. Built the PLI for the Aldec Riviera-PRO simulator

9. Fixed cosmetic spacing issue for vWave/Undertow for utf writers that display the module names too close together in the choose window, shows up when sub-modules have short names that are exactly the same length

10. Added support to utF API so utF files can go above 2147484148 bytes