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ANAHEIM, Calif. — A System Verilog Users' Forum here at the Design Automation Conference on Monday (June 13) gave a rare opportunity for users to speak out through the din of marketing messages that is growing over the battlefield between System Verliog and System C. Sponsored by Synopsys, which has a strong interest in the outcome of this contest and engineers from Freescale, ARM, and Intel described their experiences with the language. Ken Albin of Freescale said System Verilog is to a large extent formed by blending parts of the Vera language into Verilog — or the value of System Verilog to the verification process. "Our verification methodology needs object-oriented verification features, primarily to foster reuse of verification IP," Albin said. "We also need accurate functional coverage mechanisms. And we are heavily dependent on assertions. In System Verilog, we have a language that allows us to meet all these needs without multiple languages or translations. For example, we have an internal assertion language—CBV—that we have been using. We are moving the CBV assertions attached to our existing IP into System Verilog. As the language features become available in the tools, we adopt them." ARM's Alan Hunter said design facility — where the next-generation Tiger CPU core is being developed — agreed. He described an environment in which ARM's enormous legacy instruction set and functional validation suite is used in combination with functional-coverage tools and "pervasive use of assertions." Hunter also described an incremental shift-over from legacy tools. "We still use OVL for simple assertions in legacy blocks, simply because they are in place," he said. "We have been using Synopsys Native Test Bench for functional coverage. We are moving the assertions to System Verilog, and will move over from NTB to System Verilog functional coverage tools when they are avaiable in release 3.1a." While the first two speakers emphasized the verification side of the language, Matt Maidment of Intel broke with the stereotype and said that Intel is using the system-level design constructs of the new language. "Our experience is that System Verilog is simply a better Verilog," he said. "It leads to a better system design methodology, it captures design intent better, and it puts the methodology on a better evolutionary path. For example, System Verilog allows us to capture the relationships within the data and to encapsulate that knowledge so that it can be shared among the groups working on the design." Maidment emphasized the evolutionary nature of System Verilog. "With the kinds of pressures that our designs are under today, we don't have the option of making a drastic change in methodology," he declared. "We have to change by evolution, and that is what System Verilog is allowing us to do. But even with incremental change there is a challenge—to use the new constructs effectively without losing our insight into the factors that bring about design convergence

Accellera Approves Four New Design Verification Standards Business Wire, June 2, 2003 NAPA, Calif.--(BUSINESS WIRE)--June 2, 2003
Accellera, the electronics industry organization focused on language-based electronic design standards, today announced that its Board and Technical Committee members -- systems, semiconductor and design tool companies -- have approved four new standards for language-based design verification. The new Accellera standards include Property Specification Language (PSL) 1.01, Standard Co-Emulation Application Programming Interface (SCE-API) 1.0, SystemVerilog 3.1 and Verilog-AMS 2.1. Accellera's standards improve the way designers will design electronic circuits and systems in the 21st century. "Today's announcement is an exciting milestone for Accellera and system-level verification," said Accellera chairman Dennis Brophy. "Accellera members and technical teams have done an outstanding job of getting these new language-based standards approved and ready for deployment." Accellera's policy is to transfer its standards to the IEEE. More about Accellera New Standards PSL Accellera's PSL was developed to address the shortcomings of natural language forms of specification. It gives the design architect a standard means of specifying design properties using a concise syntax with clearly defined formal semantics. Similarly, it enables an RTL implementer to capture design intent in a verifiable form, while enabling the verification engineer to validate that the implementation satisfies its specification with dynamic (that is, simulation) and static (that is, formal) verification. It also provides a standard means for hardware designers and verification engineers to rigorously document the design specification. "A change is taking place in the way we design and verify our designs that will revolutionize the industry and result in the equivalent of a synthesis productivity breakthrough in verification. This change demands that we move from natural language forms of specification to forms that are mathematically precise and verifiable, and lend themselves to automation. The PSL 1.01 standard offers an opportunity to enable this huge leap in productivity of specification, design, and verification," said Harry Foster, Accellera Formal Verification Technical Committee Chair. SCE-API The SCE-API standard defines a high-speed, asynchronous, transaction-level interface between simulators or testbenches and hardware-assisted solutions such as emulation or rapid prototypes. "The SCE-API offers an intelligent interface for many types of tools," noted Brian Bailey, Accellera Interfaces Committee Chair. "Since verification requirements are increasing, in many cases, a single tool isn't enough. In these cases, a standard interface between the tools can bring the best in class tools together, and allow for better re-use of models among different design tools." For more information, please visit SystemVerilog SystemVerilog 3.1 evolves the Verilog language with powerful design and verification capabilities. It provides design constructs for architectural, algorithmic and transaction-based modeling. It adds an environment for automated testbench generation, while providing assertions to describe design functionality, including complex protocols, to drive verification using simulation or formal verification techniques. Its C-API provides the ability to mix Verilog and C/C++ constructs without the need for PLI for direct data exchange. "SystemVerilog 3.1 is a monumental effort that breaks new ground for the electronics industry and nanometer verification challenges," said Vassilios Gerousis, Accellera's Technical Committee Chairman. " It is the first hardware design verification language or HDVL standard, built on top of Verilog HDL. It was developed and approved through the cooperation of EDA companies and users alike, with more than 40 worldwide industry experts and 120 contributors." Gerousis added, "SystemVerilog 3.1 is ready for early adoption by EDA companies and customers." For more information, please visit the following sites: SystemVerilog Synthesizable High Level Constructs: SystemVerilog Testbench: SystemVerilog Assertions: SystemVerilog C/API: Verilog-AMS The Verilog-AMS language standard models mixed-signal behavior. Given the increased mixed-signal content in today's SoCs, the Verilog-AMS language helps to verify a design at the system level as well as at the block level. The 2.1 standard improves the syntax and semantics of the mixed-signal extensions to the Verilog-AMS language making it more intuitive and easier to use. Srikanth Chandrasekaran, Verilog-AMS chair, remarked, "For the next version of Verilog-AMS, we plan to investigate device modeling and RF features. As requested by the Accellera Board, we do plan to synchronize Verilog-AMS more tightly with the digital standards -- SystemVerilog and the IEEE 1364 2001." For more information, please visit About Accellera Accellera is an electronics industry organization driving the worldwide development and use of standards required by systems, semiconductor, and design tools companies that enhance a language-based design automation process. For more information, please visit Acronyms AMS Analog Mixed Signal EDA Electronic Design Automation HDL Hardware Description Language IEEE Institute of Electrical and Electronic Engineers PLI Programming Language Interface PSL Property Specification Language RTL Register Transfer Level SoC System on Chip SCE-API Standard Co-Emulation Application Programming Interface Note to Editors: Accellera acknowledges trademarks or registered trademarks of other organizations for their respective products and services. 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