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An Overview of SystemVerilog 3.1 By Stuart Sutherland, EEdesign

SystemVerilog is an extensive set of enhancements to the IEEE 1364 Verilog-2001 standard. These enhancements provide powerful new capabilities for modeling hardware at the RTL and system level, along with a rich set of new features for verifying model functionality. The primary objectives of this article are to: Present an overview of the features in the SystemVerilog 3.1 standard. Address concerns that perhaps SystemVerilog is not ready for use. It is impossible to cover all the aspects of SystemVerilog in one short article. Only some of the more significant features are presented. For those who would like to know more about the many exciting features of SystemVerilog, Accellera presented a free SystemVerilog workshop at the recent Design Automation Conference. The author of this article also presents in-depth training workshops on SystemVerilog. A problem that needed solving. For many years, the behavioral coding features of Verilog, plus a few extras such as display statements and simulation control, gave Verilog-based design engineers all they needed to both model hardware and to define a testbench to verify the model. As design sizes have increased, however, the number of lines of RTL code required to represent the design have increased dramatically. Even more significant is the increase in the amount of verification code required to test these very large designs. While modeling large designs and verification routines in traditional RT-level HDLs is still possible, the amount of coding far exceeds what can be accomplished in a reasonable amount of time. To address these problems, new design languages such as SystemC were created that could model full systems at a much higher level of abstraction, using fewer lines of code. Proprietary Hardware Verification Languages (HVLs) such as Verisity's e and Synopsys' Vera were created to more concisely describe complex verification routines (Note: company and product names are trademarked names of their respective companies). These proprietary languages solve a need, but at the cost of requiring engineering teams to work with multiple languages, and often at the expense of simulation performance. The SystemVerilog standard currently being defined by Accellera takes a different approach to solving the design and verification needs of today's multi-million gate designs. Rather than re-invent the wheel with new languages, Accellera" the combined VHDL International and Open Verilog International organizations " has defined a set of high-level extensions to the IEEE 1364 Verilog-2001 language. The definition of the SystemVerilog 3.1 standard has been completed and is expected to be released in June of this year. Accellera plans to donate the SystemVerilog extensions to the IEEE 1364 Verilog Standards Group, where it is anticipated that the extensions will become part of the next generation of the IEEE 1364 Verilog standard. SystemVerilog's roots. Accellera chose not to concoct these SystemVerilog enhancements to Verilog from scratch. That would have required re-inventing the wheel and creating a standard based on unproven, untested syntax and semantics. Instead, Accellera relied on donations of technology from a number of companies. These donations include high-level modeling constructs from the Superlog language developed by Co-Design, testbench constructs from the Open Vera language and VCS DirectC interface technology donated by Synopsys, and assertions work from several companies, including, to name just a few, OVA from Verplex, ForSpec from Intel, Sugar (renamed PSL) from IBM, and OVA from Synopsys. Over the past two years, the Accellera SystemVerilog committee and subcommittees have met two to four times each month to standardize these donations. Members of the SystemVerilog committee include experts in simulation engines, synthesis compilers, verification methodologies, members of the IEEE 1364 Verilog Standards Group, and senior design and verification engineers. Compatibility with Verilog-2001. A primary goal of the SystemVerilog standardization effort has been to ensure that SystemVerilog is fully compatible with the IEEE 1364-2001 Verilog standard. Each of the technology donations selected by the SystemVerilog committee was in a different language than Verilog. The committee carefully reviewed each and every construct and enhancement and made changes where ever necessary to ensure that all SystemVerilog enhancements were fully backward compatible with the Verilog language. All existing Verilog models should work with software tools that implement the SystemVerilog enhancements. There is one caveat to this backward compatibility. SystemVerilog adds several new keywords to the Verilog language. There is the possibility that an existing model may have used one or more of these new keywords as a regular identifier. This is a relatively minor problem that software tools can easily deal with using compatibility switches. Assertions. SystemVerilog provides special language constructs to verify design behavior. An assertion is a statement that a specific condition, or sequence of conditions, in a design is true. If the condition or sequence is not true, the assertion statement will generate an error message. SystemVerilog assertions are an integration of PSL (originally called "Sugar"), OVA, OVL, ForSpec and other assertion technologies, all of which have been donated to Accellera. The result is a single assertion language that provides a convergence of the best features of each of these assertion methodologies. A SystemVerilog assertion can test for a sequence of conditions that span multiple clock cycles. The following assertion example checks that in the FETCH state, request must be true immediately, and grant must become true one to three clock cycles later, followed by request becoming false by the next clock cycle and grant being false by the next clock cycle after that. Should this sequence not occur, the assert statement will automatically generate an error message SystemVerilog allows much more complex assertion sequences to be easily constructed than what is shown in this simple example. Special functions are also provided to check for complex expressions, such as only a single bit being set in a one-hot state machine controller. Another important feature of SystemVerilog assertions is the ability to define assertions outside of Verilog modules, and then bind them to a specific module or module instance. This allows verification engineers to add assertions to existing Verilog models, without having to change the model in any way. Interfaces. Verilog connects one module to another through module ports. This requires a detailed knowledge of the intended hardware design, in order to define the specific ports of each module that makes up the design. Several modules often have many of the same ports, requiring redundant port definitions for each module. Every module connected to a PCI bus, for example, must have the same ports defined. SystemVerilog interfaces provide a new, high level of abstraction for module connections.

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